1. Field of the Invention
The invention relates in general to a non-volatile memory device, a non-volatile memory cell thereof and method of fabricating the same, and more particularly to a non-volatile memory device with an induced source/drain, a non-volatile memory cell thereof and method of fabricating the same.
2. Description of the Related Art
The memory devices for non-volatile storage of information, such as read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), and other advanced memory devices, are currently used in the worldwide industries. The other advanced memory devices that involve more complex processing and testing procedures include electrically erasable programmable read only memory (EEPROM), flash EEPROM, and nitride read-only memory (NROM). These advanced memory devices can accomplish the tasks that ROM can't do. For example, using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device.
FIG. 1A schematically shows a cross sectional view of a conventional non-volatile memory cell. Take a NROM cell 20 for an example, the substrate 10 is implanted a source 12 and a drain 14. The top of substrate 10 lies an sandwiched structure having a nitride layer 17 between a top oxide layer 16 and a bottom oxide layer (tunneling oxide layer) 18, so known as ONO structure. The structure of NROM cell in which contains dual bit in one cell is also depicted in FIG. 1A. The two regions encircled with the dashed line denote the first bit 32 and the second bit 34. In the conventional process, the ONO layer is added over the substrate. The source/drain is then implanted, and the buried drain (BD) is formed. Following the implantation in the substrate, the polysilicon is deposited over the ONO layer of memory cell.
However, there are several drawbacks in the conventional structure and fabricating method. For example, the NROM cell with multiple oxide layers may have buried diffusion problem, as shown in FIG. 1B. In the conventional process, the phosphorus or arsenic ions are implanted and the source 12 and drain 14 are originally kept at a distance of d. After the second oxide layer grown on the first oxide layer, the source 12 and drain 14 diffuse and the distance between thereof is d′, as the dash lines 12′ and 14′ depicts. Similarly, the source 12′ and drain 14′ diffuse (as depicted by dash lines 12″ and 14″) and the distance between thereof is d″ if the third oxide layer is grown on the second oxide layer. According to the above description, it is clear that the BD over-diffusion problem may shorten the length of channel, and even result in the function failure caused by the two BD joined together, as so called ‘punch-through’. From one aspect, the punch-through problem also hinders the cell size shrinkage of such type of memory since adequate channel length has to be maintained. Moreover, dual bits in a single cell are so close that the reading process of one bit will be interfered by another bit in the same cell, as so-called ‘second-bit effect’.